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sc_inout and tristate support

Added by Mikael Strom about 4 years ago

Hi,

I've gathered that tri state is not fully implemented yet. I did notice that when building for SystemC, verilog inout ports generate sc_inout<bool>. How difficult would it be to instead use sc_inout<sc_logic> and support tristate for SystemC? In our case, it would be enough that simple continuous statements with '0', '1' , 'Z' ('X' not really needed) is supported, to avoid tons of code in the test bench to map ports.

I looked in the source for verilator, but became overwhelmed by the complexity. If this is not too difficult, i might be able to help out.

Regards, Mike


Replies (5)

RE: sc_inout and tristate support - Added by Wilson Snyder about 4 years ago

To fix this, I'd suggest:

1. Make some test cases in the test_regress directory (which will fail until this all is done)

2. Figure out the appropriate boilerplate to convert the sc_inout to the two signals verilator creates.

3. VL_ASSIGN_S* is used to assign SystemC to one verilator signal. Make a similar set of macros taking the sc_inout and all of the other signals. Change your handcrafted test in #2 to use these.

4. Make a new AstAssignScTri node type to represent this assignment.

5. Change V3Tristate to create this new AstType when it processes the tristates.

6. Change V3EmitC to output the new assignment type.

RE: sc_inout and tristate support - Added by Mikael Strom about 4 years ago

Thanks Wilson,

if this would be implemented and pass regression tests, can we expect that it goes into trunk?

Regards, Mike

RE: sc_inout and tristate support - Added by Wilson Snyder about 4 years ago

There's no guarantee that any patch is accepted, but (perhaps after a little clean) up I think everyone's has made it in.

RE: sc_inout and tristate support - Added by Slava B 5 months ago

Hi,

Is there any update on this very important feature?

Regards, Slava

RE: sc_inout and tristate support - Added by Wilson Snyder 5 months ago

Unfortunately not. One workaround is to make a wrapper module that does the conversion.

E.g. module wrap;

input foo_in;
input foo_en;
output foo_out;
wire foo = foo_en ? foo_in : 'z;
wire foo_out = foo;
    (1-5/5)