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A problem with shared Vlvbound variables

Added by James Hanlon almost 2 years ago

I've been working on a tool that uses Verilator to produce a netlist graph from the AST of a Verilog design. I've based the logic for construction of the graph on V3Gate.cpp.

It is all working well, but I've run into a problem with 'Vlvbound' variables. I have multiple calls to a particular function and they all share a single Vlvbound variable. The effect of this is that it introduces invalid paths into the netlist. I would have expected that where a Vlvbound variable is introduced in a function, each invocation of that function gets a uniquely named one. That would be consistent with variables that are used in functions.

Are Vlvbound variables expected to manifest in this way? If not, then can I work around this issue in the way I am walking the AST? Or is there a way to fix this?

The issue can be reproduced with this module:
module vlvbound_test
   (
    input logic [31:0]  i_foo_current,
    input logic [31:0]  i_foo_next,
    output logic [7:0]  o_foo_inactive,
    output logic [7:0]  o_next_foo_inactive
    );

  localparam CONTEXT_ID_NUM = 7;
  typedef logic [CONTEXT_ID_NUM-1:0] foo_active_t;

   function  automatic foo_active_t rd_sts_inactive
    (
     input logic [31: 0] foo
     );
       foo_active_t ret;
       integer           i;
       logic [1:0]       tmp;
       for (i=0 ; i < 7; i++)
        begin
            tmp    = foo >> (i*2);
            ret[i] = (tmp == 0) ;
        end
       return ret;
   endfunction

   assign o_foo_inactive       = rd_sts_inactive(i_foo_current);
   assign o_next_foo_inactive  = rd_sts_inactive(i_foo_next);

endmodule
Running:
verilator --lint-only +1800-2012ext+.sv --debug
Then looking at the dot graph or tree dump at the gate stage.

vlvbound.sv (755 Bytes)


Replies (2)

RE: A problem with shared Vlvbound variables - Added by Wilson Snyder almost 2 years ago

The vlbound's don't really have any usefulness related to visualizing, I'd ignore them or have a flag to not create them.

Selishly I like your using verilator but wonder if a synthesis toolchain would help you out more.

Are you by chance using this to improve http://digitaljs.tilk.eu/

If so like it and congrats on your recent mention on hackaday.

RE: A problem with shared Vlvbound variables - Added by James Hanlon almost 2 years ago

The vlbound's don't really have any usefulness related to visualizing, I'd ignore them or have a flag to not create them.

Thanks Wilson, that's useful to know. I think it will be simpler then to remove most of the optimisations before I output the netlist graph.

Selishly I like your using verilator but wonder if a synthesis toolchain would help you out more.

It's very much a source code tool, to be used in conjunction with synthesis tools.

Are you by chance using this to improve http://digitaljs.tilk.eu/

Nope, nothing to do with me. Nice project though!

    (1-2/2)