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detecting edges in an initial block

Added by Art. FR about 1 year ago

Dear developers,

I was wondering if you could support the execution of the following code (which is supported by cadence):
initial
     begin
       @(posedge clk);
       $display("I saw one posedge");
       @(posedge clk);
       $display("I saw another posedge");
       @(posedge clk);
       $finish;    
      end

This would allow us to develop simple testbenches in systemVerliog and keep the C++ code to a bare minimum (i.e., just a master clock).

Another nice feature would be fork join statements inside an initial block.

Would that represent to much of a development challenge?

Thanks a lot and keep up the great work. Verilator is really awesome.


Replies (1)

RE: detecting edges in an initial block - Added by Wilson Snyder about 1 year ago

Verilator is a cycle based simulator, not an event based simulator, so this is unlikely to be supported anytime soon. See also bug235 and bug236.

The way that is supported is to make a little FSM, e.g..

integer state = 0;
  always @ (posedge clk) begin
    if (state==0) begin state++; $display("I saw one posedge"); end
    else if (state==1) begin state++; $display("I saw one posedge"); end
    else if (state==2) begin state++; $display("I saw another posedge"); end
    else if (state==3) begin state++; $finish; end
  end
    (1-1/1)