Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

One eval() method per clock domain ?

Added by Frederic Requin 5 months ago

Hello,

in multiple clock domains designs, I am wondering if it would be more efficient to have one eval() method per clock (or even two : rising and falling edges ?).

To generate clocks with arbitrary frequency, I have this special C++ object : http://github.com/fredrequin/fpga_1943/tree/master/verilator/clock_gen .

If I connect the eval() methods to the clock generator through call-backs, I should get some nice runtime improvement.

Any thoughts ?

Regards,

Frederic Requin


Replies (1)

RE: One eval() method per clock domain ? - Added by Wilson Snyder 5 months ago

Multiple evals would save some branch instructions. There's two problems though, first is any logic downstream which feeds from multiple edges would be in multiple evals. Second multiple clocks may arrive at the exact same time (e.g. gated clocks) and for correctness (to avoid races) must be part of the same eval.

    (1-1/1)