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enhancement to support SystemVerilog for loop multiple vars

Added by Jon Stahl 3 months ago

Hi,

I would like to start using Verilator more generally at my company and have found v4.020 supports almost all our code except for multiple var for loops e.g./

always_comb
  begin
 for (int i=0,j=0; j<4; i=i+2,j++)
   begin
      if ( (!level1[i][7] && level1[i+1][7]) || (level1[i+1][7] && (level1[i+1][6:0] < level1[i][6:0])) )
        level2[j] = level1[i+1];

I'm looking into enhancements to support this. Would appreciate any guidance that can be offered.

Regards, Jon


Replies (1)

RE: enhancement to support SystemVerilog for loop multiple vars - Added by Wilson Snyder 3 months ago

Hmm, there was some work on this that seems to have gotten lost in the cracks.

https://www.veripool.org/boards/2/topics/2692?r=2908

Will post there.

    (1-1/1)