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VHDL Support

Added by Sebastien Van Cauwenberghe over 8 years ago

Hi All,

I've read that there is an experimental VHDL support in verilator. Is it true ? If yes, where can I find it ?

I'd like to contribute for that support.

The only free VHDL simulator is very good but very slow and cannot be used for big designs like SoC.

Thanks in advance

Regards Sebastien


Replies (11)

RE: VHDL Support - Added by Wilson Snyder over 8 years ago

Not that I know of. Several people have talked about adding the parsing, but nothing has come from it yet. If you're game to start on it I know it would be well appreciated.

RE: VHDL Support - Added by Sebastien Van Cauwenberghe over 8 years ago

Ok.

Do you have pointers on how to get started ? Documentation of the internal structures and so on ? It should be ok for Bison/Flex, it can take some time though...

Regards Sebastien

RE: VHDL Support - Added by Wilson Snyder over 8 years ago

That would be awesome!

There is documentation on the tree files in internals.txt in the git repository.

What I would do is to first make a little hello world test, then get just that to pass, that shouldn't be hard and will lead to quick gratification :) and more frequent merges back to the trunk. To do so you'd need a new flex and bison rules based on the ones already there for verilog - rather than copy the verilog.l/y files I would suggest just extending the existing grammars.

Adding more of the language you can probably find an open source bison/flex parser somewhere either to use directly or as a reference. Most VHDL constructs should map directly to verilog AST tree nodes, those that don't would require adding a new classes, then processing them, probably making them more verilog-ish early on so that the information doesn't need to last very long.

There's certain to be places where the internals make strong assumptions about Verilog; as those come up let me know and I'll help generalize the code.

RE: VHDL Support - Added by Sebastien Van Cauwenberghe over 8 years ago

Thanks for the info.

I'll first see the first thing to parse because the hello world is not that straightforward. Are you sure you wanna merge the two grammars ? VHDL has an awful syntax from what I saw and requires a GLR parser...

What do we do with the libraries ? and the user defined types ?

Regards Sebastien

RE: VHDL Support - Added by Wilson Snyder over 8 years ago

I'm definitively not sure I want to merge the grammars :) It seemed like it might be easier as they would then be able to share the /*verilator*/ and similar common parsing, but it's hard to know without getting into it; a easy compromise may be to put it in a separate parser and have a common #include'ish file for the grammar. (Note the grammar goes through bisonpre, so we can add includes or whatever as needed). If it's a true GLR that's fine as bison can now handle GLR, and FWIW SystemVerilog would have a bunch fewer hacks in the grammar if it went to GLR.

I'm not sure which issue you are referring to for the libraries. As for getting them we should be able to either use the IEEE versions and/or the ones from icarus. The parser would then know to resolve them by looking into $VERLATOR_ROOT/include/vhdl or some such.

RE: VHDL Support - Added by Sebastien Van Cauwenberghe over 8 years ago

VHDL doesn't support C style comments, those comments will need another syntax anyway ;).

VHDL has lots of different ways to represent signals and variables. You are right, for the libraries, they should be translatable...

I'll make some trials and see what is the cleanest way to do.

RE: VHDL Support - Added by Wilson Snyder over 8 years ago

VHDL doesn't support C style comments, those comments will need another syntax anyway

True, though that's easily hidden in the lexer.

BTW we didn't talk about preprocessing. It would be nice to someday allow mixed VHDL+Verilog parsing, so I'd suggest that the file name resolver know how to automatically look for .vhd[l] extensions in addition to .v. (Change libExt to be libExtV, and add libExtVHDL, then have V3Options::filePath use both.) When V3PreShell::preprocOpen gets called it would ask V3Option if the filename ends in a libExtVHDL extension (.vhd/.vhdl) and then would set a flag telling the preprocessor to do almost nothing, and then pass the flag to the parser to either invoke the special VHDL rules, or the entirely new grammar. (Another idea rather than a flag would be to insert into the parse stream a "`vhdl" directive, which the verilog (pre)parser would use to change parse modes. That's cool as it may allow language switching at a very fine level.)

RE: VHDL Support - Added by Sebastien Van Cauwenberghe over 8 years ago

True, though that's easily hidden in the lexer.

Indeed, it can be hidden.

It would be nice to have a mixed language simulator. I think it is ok to switch between grammar/grammar rules depending on the file extension (.v/.vhd[l]). But I'm not sure a finer grained control over the language switching into files is required. It will just make all the things more complicated and, no sane people mixes VHDL and Verilog in the same file :). I'm not sure synthesizers even support that...

RE: VHDL Support - Added by Wilson Snyder over 8 years ago

BTW, This is sort of a language switch, even if not between verilog & vhdl.

`vhdl
 -- ...
`verilator_config
 //....
`systemc_header
 #include "foo.h" 
`vhdl

RE: VHDL Support - Added by Sebastien Van Cauwenberghe over 8 years ago

If you say so. I never used that switch before...

Please note that I do that on my spare time, now that I have some stuff to start with. I come back to you if I have questions...

Sebastien

RE: VHDL Support - Added by Sebastien Van Cauwenberghe over 8 years ago

Hi All, Wilson,

I began writing the grammar, unfortunately, it will be a GLR one because of some nice things of VHDL :).

Is it an easy task to modify the current grammars (without breaking everything) to be GLR. Is there not too much work in the lexer part, because with GLR, we cannot assume that the lexer and the parser are in sync because the actions are deferred until only one parser remains if they split. If your grammars are LALR, there is no problems, I think.

Once the grammar parses simple VHDL code, like the examples of ASIC-World. I'll try to create the AST nodes from the parser. I come back to you when I'm done with this task.

In the beginning, I'll support basic things of the ieee library inside C++.

For some things that are VHDL specific, like type definitions, functions, operators overloading, ... We will see as the work progresses.

Sebastien

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