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Issues: verilator/verilator

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#4298 opened Jun 17, 2023 by wsnyder
Open
Support full UVM -cc code generation
#1538 opened Oct 6, 2019 by veripoolbot
Open 42
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293 Open 2,938 Closed
293 Open 2,938 Closed
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Issues list

No warning/error if a signal is driven by both concurrent and continuous assignment new New issue not seen by maintainers
#5052 opened Apr 16, 2024 by goekce
Verilation makefile should not use $(info Archive ...). new New issue not seen by maintainers
#5051 opened Apr 16, 2024 by goekce
1
Internal Error: Variable inlining should make this impossible with v5.024 new New issue not seen by maintainers
#5050 opened Apr 15, 2024 by wltr
Add error when display a compound type area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5049 opened Apr 15, 2024 by goekce
4
Wires driven through virtual interface traced improperly area: tracing Issue involves tracing status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5044 opened Apr 10, 2024 by RootCubed
2
Verilator not handling hierarchical signal references correctly area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API status: discussion Issue is waiting for discussions to resolve
#5041 opened Apr 9, 2024 by slmnemo
1
Support generating SAIF file for power estimation status: discussion Issue is waiting for discussions to resolve
#5037 opened Apr 5, 2024 by ayanbanrj
1
Verilator's vpiStringVal implementation masks byte values of 32 and 0 area: vpi/dpi/api Issue involves VPI, DPI, or verilated.h interface API status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5036 opened Apr 4, 2024 by mjeje
3
Fatal error: 'experimental/coroutine' file not found, on macOS using Clang latest area: portability Issue involves operating system/compiler portability status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5030 opened Mar 31, 2024 by selimsandal
2
Being able to specify a zero width in an indexed part-select operation violates LRM area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5028 opened Mar 30, 2024 by chykon
2
Class specialization is ignored for associative array as a class type parameter area: elaboration Issue involves elaboration phase status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5022 opened Mar 27, 2024 by esynr3z
Fix comparison of data types status: asked reporter Bug is waiting for reporter to answer a question
#5005 opened Mar 20, 2024 by tastynoob
1
11
"Error-LIFETIME" when using a clocking block inside a submodule status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#5004 opened Mar 19, 2024 by abarajithan11
1
add reflection adjacent capability to model output
#5002 opened Mar 19, 2024 by ct-clmsn
6
Internal error on using constant variable within array assignment status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4998 opened Mar 18, 2024 by esynr3z
1
NBA order graph of t_timing_nba is incorrect area: scheduling Issue involves scheduling/ordering of events status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4993 opened Mar 16, 2024 by gezalore
2
Declaring a constant with simultaneous initialization may result in an error depending on the lifetime and context status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4992 opened Mar 16, 2024 by chykon
1
error: invalid types'WData {aka unsigned int}[unsigned int]"for array subscript status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4989 opened Mar 16, 2024 by futurehome
10
Is selectable diagnostic message for $finish supported? type: feature-IEEE Request to add new feature, described in IEEE 1800
#4981 opened Mar 14, 2024 by dominiksalvet
3
Fix evaluating final blocks on fatal status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4980 opened Mar 14, 2024 by dominiksalvet
2
Linter allows commas in instance parameters where they are not allowed in Verilog area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned'
#4979 opened Mar 13, 2024 by paul-demo
3
Tracking Signal Change Triggers in Verilator area: tracing Issue involves tracing status: discussion Issue is waiting for discussions to resolve
#4973 opened Mar 13, 2024 by ThePerfectComputer
3
Mac OS missing FlexLexer.h status: assigned Issue is assigned to someone to work on
#4970 opened Mar 12, 2024 by ct-clmsn
Unexpected Significant Performance Degradation on Movement of Code status: discussion Issue is waiting for discussions to resolve
#4967 opened Mar 12, 2024 by Karl-Han
17
Optimization for Conditional Statement status: asked reporter Bug is waiting for reporter to answer a question
#4964 opened Mar 11, 2024 by europe2024
3
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