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Support "logic" keyword #101
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Original Redmine Comment Thanks for trying to add this! Here's the rough steps - I'll be pretty detailed since this is your first look at the code, but even so I probably missed something so feel free to ask if you need more help. Download via git, if you haven't yet. Add a test by copying test_regress/t/t_EXAMPLE.* to t_var_logic.* (or another name). See it fail by typing "test_regress/t/t_var_logic.pl --v3". Add yLOGIC to verilog.l - see Verilog-Perl VParseLex.l. Add yLOGIC to top of verlog.y - see Verilog-Perl VParseBison.y If verilator had types you'd then add yLOGIC in a similar place to where it is in the Verilog-Perl version, but that code isn't there yet. Instead simply replicate the line that uses yREG and change yREG to yLOGIC. Build with "make" Check the new test works. Do a "make test" to make sure all other tests work (you'll need SystemC and SystemPerl for this - otherwise ignore the related failures.) Commit your results locally with "git commit -a", then send me or post here the result of "git diff origin" (When you start doing more you might want to read a tutorial on git.) |
Original Redmine Comment Hi, thanks for the instructions. The git diff is attached. When I run 'make test' I get the following error:
I'm pretty sure that both SystemC and SystemPerl are installed correctly (and the stuff I've added makes no difference.) |
Original Redmine Comment Great, I pushed this to git. (Use git pull to see it.) The only change was I don't generally comment out old code, and I added a note to Changes and the manual. Please file another bug if you'd like to do more! (Alas I can't promise they'll be this easy ;) |
Original Redmine Comment Forgot to reply to your problem - I think Verilog-Perl isn't installed, which is why you got that error. |
Original Redmine Comment In 3.713. |
Author Name: Alex Duller
Original Redmine Issue: 101 from https://www.veripool.org
Original Date: 2009-07-16
Adding support for SystemVerilog logic reserved word
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