Author Name: Eitan Golan
Original Redmine Issue: 1010 from https://www.veripool.org
Original Date: 2015-12-07
Original Assignee: Wilson Snyder (@wsnyder)

I have a module:

module my_module (
input [2:0] x1 ,
input x2 ,
input [7:0] x3 ,
input [5:0] y1 ,
input y2 ,
output [3:0] o1 ,
output o2
);

At the the instance of my_module I want to tie low all the x* inputs, so my_top.v looks like this:

wire [32:0] tie_low = 32'd0;

/* my_module AUTO_TEMPLATE(
.x. (tie_low[]),
);*/

I get the following instance:

my_module my_inst
(/AUTOINST/
// Outputs
.o1 (o1[3:0]),
.o2 (o2),
// Inputs
.x1 (tie_low[2:0]), // Templated
.x2 (tie_low), // Templated
.x3 (tie_low[7:0]), // Templated
.y1 (y1[5:0]),
.y2 (y2));

There is a problem with x2 input, since it is a single bit (not a bus) it is assigned the wire "tie_low" without any dimensions.
The correct verilog assignment should be:

.x2         (tie_low[0]),       // Templated

Is there a way to assign it correctly with bit[0] ?