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I instantiate a module with many input and outputs.
I want that all inputs will have their name preceded by smp_OrigInputName,
and I want all output to have their name preceded by pre_OrigOutputName.
Is there an easy way to do it?
Thanks.
Yoram
The text was updated successfully, but these errors were encountered:
Author Name: Yoram Stern
Original Redmine Message: 1779 from https://www.veripool.org
Hi.
I instantiate a module with many input and outputs.
I want that all inputs will have their name preceded by smp_OrigInputName,
and I want all output to have their name preceded by pre_OrigOutputName.
Is there an easy way to do it?
Thanks.
Yoram
The text was updated successfully, but these errors were encountered: