module top(
  input        a[1],
  output logic b[1],
  input        clk,
  input        en
);
    always_ff @(posedge clk)
        b <= en ? a : b;
endmodule

     // Variables
     VL_SIG8(__Vdlyvval__b__v0[1],0,0);
     //char  __VpadToAlign5[3];
     // Body
     // ALWAYS at a.sv:7
     __Vdlyvval__b__v0 = ((IData)(vlTOPp->en) ? vlTOPp->a                    //this line produces compiler error: incompatible types in assignment of CData to CData [1]
        [0U] : vlTOPp->b[0U]);
     // ALWAYSPOST at a.sv:8
     vlTOPp->b[0U] = __Vdlyvval__b__v0;                                      //this line produces compiler error: invalid conversion from CData* to CData