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When a wire (bus) is created due to AUTOINST + templates and then referred to using AUTOOUTPUTEVERY, the object is defined twice - once in the port declaration and once as a wire.
This is seen as a re-declaration, which is flagged as a warning in (some?) commercial tools.
Can anyone please suggest a fix/workaround?
Thanks!
PS: Here's an example - the offending signal is "stage_2".
module test (/*AUTOARG*/
// Outputs
stage2_bus, stage3_bus,
// Inputs
stage1_bus
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output logic [7:0] stage3_bus; // From i_second of sub_module.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic [7:0] stage1_bus; // To i_first of sub_module.v
// End of automatics
/*AUTOOUTPUTEVERY("^stage")*/
// Beginning of automatic outputs (every signal)
output logic [7:0] stage2_bus; // From i_first of sub_module.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [7:0] stage2_bus; // From i_first of sub_module.v
// End of automatics
/*AUTOREG*/
/* sub_module AUTO_TEMPLATE
(
.i_\(.*\) (stage1_\1[]),
.o_\(.*\) (stage2_\1[]),
); */
sub_module i_first (/*AUTOINST*/
// Outputs
.o_bus (stage2_bus[7:0]), // Templated
// Inputs
.i_bus (stage1_bus[7:0])); // Templated
/* sub_module AUTO_TEMPLATE
(
.i_\(.*\) (stage2_\1[]),
.o_\(.*\) (stage3_\1[]),
); */
sub_module i_second (/*AUTOINST*/
// Outputs
.o_bus (stage3_bus[7:0]), // Templated
// Inputs
.i_bus (stage2_bus[7:0])); // Templated
endmodule // test
module sub_module (/*AUTOARG*/
// Outputs
o_bus,
// Inputs
i_bus
);
input logic [7:0] i_bus ;
output logic [7:0] o_bus ;
assign o_bus = i_bus;
endmodule // sub_module
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-01-21T03:13:26Z
This is related to the order of AUTOs being processed. Basically AUTOOUTPUTEVERY is pretty fragile and was intended only for a debug aid.
I tried a fix back near when you filed this, and an attempted fix broke other tests, so more work is needed. I haven't gotten back to figuring out a more complicated fix, so wanted to reply before more time passes.
Author Name: Hanan Moller
Original Redmine Issue: 1019 from https://www.veripool.org
Hello,
When a wire (bus) is created due to AUTOINST + templates and then referred to using AUTOOUTPUTEVERY, the object is defined twice - once in the port declaration and once as a wire.
This is seen as a re-declaration, which is flagged as a warning in (some?) commercial tools.
Can anyone please suggest a fix/workaround?
Thanks!
PS: Here's an example - the offending signal is "stage_2".
The text was updated successfully, but these errors were encountered: