Original Redmine Comment
Author Name: Johan Bjork
Original Date: 2016-01-19T00:37:10Z

It seems to happen when an initial block references something that gets passed through at least one module. A single level works fine (ie, replace SetStuff with "tester" in the below example and it works

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.

module t (/*AUTOARG*/);

    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire [31:0]		O_out;			// From test of Test.v
    // End of automatics

    SetStuff test (/*AUTOINST*/
	      // Outputs
	      .O_out			(O_out));

    initial begin
       if (O_out != 32'h4) $stop;
       $write("*-* All Finished *-*\n");
       $finish;
    end

endmodule

module SetStuff
  (
    output [31:0] O_out
    );

    tester t5
    (
  	.O_out(O_out)
	 );

endmodule

module tester
    (
     output [31:0] O_out
     );
    assign O_out = 4;
endmodule

```

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-01-21T03:24:31Z

When the inliner is working, it flattens the variable, so the test works.

When not, there's two initial statements, with a wire that must propagate results between them.

Verilog doesn't guarantee ordering between initial statements, much less with a continuous assignment in the middle, so either behavior is legal.

With other then verilator, an e.g. "#1;" would be required to let things propagate. In verilator tests, I generally use an "always @ (posedge clk)" around the value and $finish, for this exact ordering reason.

Original Redmine Comment
Author Name: Johan Bjork
Original Date: 2016-01-21T03:27:43Z

Perfect, thanks for the great explanation.