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SV interface bug #1026

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veripoolbot opened this issue Jan 20, 2016 · 1 comment
Closed

SV interface bug #1026

veripoolbot opened this issue Jan 20, 2016 · 1 comment
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resolution: no fix needed Closed; no fix required (not a bug)

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Author Name: Thomas J Whatson
Original Redmine Issue: 1026 from https://www.veripool.org
Original Date: 2016-01-20
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-01-21T00:11:19Z

  1. This is a verilator not verilog-mode bug. Also please don't post to other sites, just attach the tar here.

  2. You're driving the clock high at the same time as the input signal, therefore it is of course getting latched the same time. Instead drive the inputs high on e.g negedges.

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