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Issue #1036

Reset fails to respond when driven from vector containing clock enable

Added by Neil Turton about 3 years ago. Updated about 3 years ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
WrongRuntimeResult
% Done:

0%


Description

In the attached test, the active low reset output fails to go high when the active high input goes low.

There are several work-arounds. One is to define the FIXIT macro which modifies the test code. Another is to remove the clock_enable comment. Another is to delete slave_clk.

To reproduce, save the attached files in the current directory and run the commands: make ./obj_dir/Verror9

error9.v (1.09 KB) Neil Turton, 02/14/2016 03:07 PM

error9.c View (679 Bytes) Neil Turton, 02/14/2016 03:07 PM

Makefile (258 Bytes) Neil Turton, 02/14/2016 03:07 PM

History

#1 Updated by Neil Turton about 3 years ago

There's a formatting problem in the commands to reproduce the issue. There should be two commands (separated by a new line which got removed). So, "make ; ./obj_dir/Verror9" would do.

#2 Updated by Wilson Snyder about 3 years ago

  • Status changed from New to Confirmed

Attributes such as the clock enables and clocks themselves are propagated signal-by-signal rather than bit-of-signal. So what's going on here is the clock enable attribute also gets associated with the reset. This is certainly a bug, but fairly fundamental so unfortunately is unlikely to be resolved any time soon, sorry.

#3 Updated by Todd Strader about 3 years ago

This looks very similar to a problem we had with vectors of clocks:

http://www.veripool.org/issues/1009-Verilator-Non-cutable-ordering-loop-when-using-an-array-of-clocks

I've been slacking on cleaning this up for pushing back upstream, but the GitHub link has the code that we are currently using to address the issue. I haven't tried your code, however, my suspicion is that it will not work for you. But it should be trivial to apply the same technique for clock enable signals (as opposed to clocks).

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