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Issue #1037

Verilator truncates statement incorrectly for pattern assignments

Added by Johan Bjork almost 2 years ago. Updated almost 2 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
WrongRuntimeResult
% Done:

0%


Description

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.

module t (clk);
   input clk;
   typedef struct packed {
      logic [2:0] _foo;
      logic [2:0] _bar;
   } struct_t;

   logic [2:0] meh;
   struct_t param;
   localparam integer twentyone = 21;

   assign param = '{
      _foo: twentyone % 8 + 1,
      _bar: (twentyone / 8) + 1
   };
   assign meh = twentyone % 8 + 1;
   initial begin
      $display("param: %d, %d, %b, %d", param._foo, param._bar, param, meh);
      $write("*-* All Finished *-*\n");
      $finish;
   end

endmodule

yields param: 0, 0, 000000, 6 expected results: param: 6, 3, 110011, 6

History

#1 Updated by Wilson Snyder almost 2 years ago

  • Category set to WrongRuntimeResult
  • Status changed from New to Resolved
  • Assignee set to Wilson Snyder

Fixed in git towards 3.881.

#2 Updated by Johan Bjork almost 2 years ago

thanks!

#3 Updated by Wilson Snyder almost 2 years ago

  • Status changed from Resolved to Closed

In 3.882.

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