// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.

module t (clk);
    input clk;
    typedef struct packed {
       logic [2:0] _foo;
       logic [2:0] _bar;
    } struct_t;

    logic [2:0] meh;
    struct_t param;
    localparam integer twentyone = 21;

    assign param = '{
       _foo: twentyone % 8 + 1,
       _bar: (twentyone / 8) + 1
    };
    assign meh = twentyone % 8 + 1;
    initial begin
       $display("param: %d, %d, %b, %d", param._foo, param._bar, param, meh);
       $write("*-* All Finished *-*\n");
       $finish;
    end

endmodule