Author Name: Yaacov Marko
Original Redmine Message: 1823 from https://www.veripool.org

Hi,
I'm having these two modules:
module_with_outputs (
output [1:0] sig1,
output [3:0] sig2
)

module_with_inputs (
input [3:0] sig1,
input [3:0] sig2
)

I'm trying to write an auto_template for instancing the second module ('module_with_inputs') to concatenate the missing MSBs for sig1:
.sig1 ({2'b0,sig1[1:0]}),
.sig2 (sig2[3:0]),

Can you please help me writing this template? I can't find a way to pass the 'module_with_inputs' template the information regarding the signals width of 'module_with_outputs'.

Thanks!