Author Name: steven prigg
Original Redmine Issue: 1042 from https://www.veripool.org

I have a structure defined:

typedef struct packed {
logic [15:0] ESR;
logic [15:0] LS;
logic [15:0] LE;
logic [15:0] OR0;
logic [15:0] OR1;
logic [15:0] OR2;
logic [15:0] ORA;
} regs_struct;

this then forms a port definition of a module (as an output):

module syb_registers (
output regs_struct regs, // registers passed out as structure

when trying to assign to regs.ESR in the following way:
assign regs.ESR = {ESR_int[15:7],ESP};

where ESP[6:0] and ESR_int[15:0] are driven from clocked always@ blocks, the assignment fails even though ESR_int and ESP present the correct values.
i.e. regs.ESR is always '0

a workaround is:
wire [15:0] ESR_collected;
assign ESR_collected[15:7] = ESR_int[15:7];
assign ESR_collected[6:0] = ESP;
assign regs.ESR = ESR_collected;

here the assignment to regs.ESR is successful.

The observed behaviour differs from simulation results from leading CAD vendors.