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indention after 'interface class ... endclass' is one level too deep #1047

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veripoolbot opened this issue Mar 17, 2016 · 2 comments · Fixed by #1768
Closed

indention after 'interface class ... endclass' is one level too deep #1047

veripoolbot opened this issue Mar 17, 2016 · 2 comments · Fixed by #1768
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Author Name: Alex Reed
Original Redmine Issue: 1047 from https://www.veripool.org

interface class ic;
...
endclass
// this should indent to left margin, but indents one stop to right
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Original Redmine Comment
Author Name: Alex Reed
Original Date: 2016-03-17T17:05:50Z

interface class ic;
  ...
endclass
  // this should indent to left margin, but indents one stop to right

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-19T13:32:22Z

Still a problem, perhaps someone would like to contribute a patch?

gmlarumbe added a commit to gmlarumbe/verilog-mode that referenced this issue May 20, 2022
@gmlarumbe
Fix indentation after 'interface class...endclass' (issue veripool#1047)
580b57f 
Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
gmlarumbe added a commit to gmlarumbe/verilog-mode that referenced this issue May 20, 2022
@gmlarumbe
Fix indentation after interface class (bug veripool#1047)
5b58785 
Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
@gmlarumbe gmlarumbe mentioned this issue May 20, 2022
Merged
gmlarumbe added a commit to gmlarumbe/verilog-mode that referenced this issue May 20, 2022
@gmlarumbe
Fix indentation after interface class (bug veripool#1047)
fbcd67c 
Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
wsnyder pushed a commit that referenced this issue May 20, 2022
@gmlarumbe
Fix indentation after interface class (#1047) (#1768).
c6e0d3f 
* verilog-mode.el (verilog-backward-sexp, verilog-forward-sexp, verilog-leap-to-class-head, verilog-leap-to-head):
Fix indentation after interface class (#1047) (#1768). Reported by Gonzalo Larumbe.

Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
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Fix indentation after interface class (bug #1047) gmlarumbe/verilog-mode
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