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Issue #1049

Do not overwrite existing assignments in new_contassign().

Added by Stefan Tauner over 1 year ago. Updated over 1 year ago.

Status:
Closed
Priority:
Normal
Assignee:
-
% Done:

100%


Description

See attachment

0001-Do-not-overwrite-existing-assignments-in-new_contass.patch View (1.69 KB) Stefan Tauner, 03/18/2016 03:37 PM

History

#1 Updated by Stefan Tauner over 1 year ago

Oh, and you probably want to do the same to new_defparam(), possibly new_cell() and maybe even others. I did not check anything besides new_contassign().

#2 Updated by Wilson Snyder over 1 year ago

  • Status changed from New to Feature

Fixed in git towards 3.419. Thanks for the patch, though I did it a bit differently as was worried having a retry loop has a risk of performance problems.

#3 Updated by Wilson Snyder over 1 year ago

  • Status changed from Feature to Resolved

#4 Updated by Stefan Tauner over 1 year ago

I noticed that you often go that way (i.e. adding fields when other solutions exist) in Verilog-Perl. Have you ever benchmarked those approaches? My understanding of current architectures is that memory latency eats up pretty many optimizations using in-application caching. Verilog-Perl already has a quite huge memory footprint already and adding more fields for things that are in very few cases used at all (Since when was this particular case broken? Did it ever work?) does not help with that.

Anyway, any fix in this case is welcomed so thanks a lot for that! I hope to be able to work on upstreaming the vector patch soon-ish (but I do so since December so... ;)

#5 Updated by Wilson Snyder over 1 year ago

  • Status changed from Resolved to Closed

In 3.420.

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