Do not overwrite existing assignments in new_contassign().
#4 Updated by Stefan Tauner over 1 year ago
I noticed that you often go that way (i.e. adding fields when other solutions exist) in Verilog-Perl. Have you ever benchmarked those approaches? My understanding of current architectures is that memory latency eats up pretty many optimizations using in-application caching. Verilog-Perl already has a quite huge memory footprint already and adding more fields for things that are in very few cases used at all (Since when was this particular case broken? Did it ever work?) does not help with that.
Anyway, any fix in this case is welcomed so thanks a lot for that! I hope to be able to work on upstreaming the vector patch soon-ish (but I do so since December so... ;)
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