Extra "v." in full signal pathnames
In a design where "--top-module toplevel" and "--prefix toplevel" are both specified on the verilator command line after "--cc", if the toplevel module instantiates a module named "leveltwo" with signal "a", Verilator currently has the full signal path to "a" as
This is non-obvious from the documentation, especially since no other simulator I know of (Icarus Verilog, Synopsys VCS, Cadence NC_verilog, Mentor Questa) inserts a non-existent module instance name into the hierarchy of the full pathname.
If this is intentional, perhaps an explanation in the documentation would help others avoid my surprise.
If this is un-intentional, could this be fixed to behave as other Verilog simulators?
#2 Updated by Wilson Snyder 11 months ago
- Category set to Unsupported
- Status changed from New to Resolved
- Assignee set to Wilson Snyder
Fixed in git towards 3.883.
BTW if you instantiate the model with name "BAR" you'll still see the name "BAR.toplevel.leveltwo.a". BAR represents the name of the thing above, e.g. your testbench so is outside the scope of Verilator itself. e.g. see all the regressions which "top.t" is now correct for both Verilator and others - top is either the test C++ wrapper for Verilator, or for other simulators a verilog test wrapper. If this still causes a mess for you, please describe how you use it.
#4 Updated by Arthur Kahlich 10 months ago
First, thanks for this. It gets rid of a hack and a headache in my debugger interface, which calls DPI-C functions that use VPI to access signals in the model.
Your description indicates to me that it will work as I expect. Of course, I still need to try it out, which I will do shortly.
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