Using AUTOs with parameterized types #1061

veripoolbot · 2016-05-25T14:19:04Z

Author Name: Brad Dobbie
Original Redmine Issue: 1061 from https://www.veripool.org
Original Date: 2016-05-25
Original Assignee: Wilson Snyder (@wsnyder)

I've found some interesting use cases for parameterized types, and I could use some help from Verilog-mode to make them more useful.

Can Verilog-mode be made to declare AUTOINPUT/AUTOOUTPUT/AUTOLOGIC signals using the correct type? In the past, I've used verilog-auto-inst-param-value to have AUTOINST replace parameters with the parameter value. Perhaps a similar substitution can be made around types.

In my example below, b0/y0 and b1/y1 can be handled by replacing "TYPE_T" with the value passed (foo_t or logic [7:0], respectively). The b2/y2 is more complex, where as "TYPE_T" should be replaced with its default logic[WIDTH-1:0] and then further processed to replace "WIDTH-1" with 7 (or WIDTH with 8).

typedef logic [7:0] foo_t;
module ptype
  (
    // Ports should be declared as follows
    //input  foo_t       a
    //output foo_t       y0,
    //output logic [7:0] y1,
    //output logic [7:0] y2,

    /*AUTOINPUT*/
    // Beginning of automatic inputs (from unused autoinst inputs)
    input TYPE_T		a,			// To b0 of ptype_buf.v, ...
    // End of automatics

    /*AUTOOUTPUT*/
    // Beginning of automatic outputs (from unused autoinst outputs)
    output TYPE_T	y0,			// From b0 of ptype_buf.v
    output TYPE_T	y1,			// From b1 of ptype_buf.v
    output TYPE_T	y2			// From b2 of ptype_buf.v
    // End of automatics

    );

    ptype_buf #(.TYPE_T(foo_t)) b0
      (// Outputs
       .y				(y0),
       /*AUTOINST*/
       // Inputs
       .a				(a));

    ptype_buf #(.TYPE_T(logic [7:0])) b1
      (// Outputs
       .y				(y1),
       /*AUTOINST*/
       // Inputs
       .a				(a));

    ptype_buf #(.WIDTH(8)) b2
      (// Outputs
       .y				(y2),
       /*AUTOINST*/
       // Inputs
       .a				(a));

endmodule

module ptype_buf
  #(parameter WIDTH = 1,
     parameter type TYPE_T = logic [WIDTH-1:0])
    (output TYPE_T y,
     input  TYPE_T a);
    assign y = a;
endmodule

// Local Variables:
// verilog-typedef-regexp: "_[tT]$"
// verilog-auto-inst-param-value:t
// End:

The text was updated successfully, but these errors were encountered:

veripoolbot · 2016-07-24T20:45:18Z

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-07-24T20:45:18Z

Thanks for the suggestion. Made this new behavior the default unless verilog-auto-inst-param-value-type is nil.

Fixed in git, 2016-07-24-cdd9115-vpo.

cswmeta · 2023-11-21T20:29:13Z

I have tried this feature and it works with the example code.

I have a case where parameterized types work properly when the child module is declared in the same file as its parent. However, if I move the child module to its own file, then the parameter type is not correctly reflected in the AUTOINPUT/AUTOOUTPUT declarations, and the comments in the module instance now seem to think the parameterized port types are Interfaces instead of ports.

Any help to point out what I'm doing wrong is most appreciated.

Here is the example file where it works correctly:

module test
(
  /*AUTOINPUT*/
  // Beginning of automatic inputs (from unused autoinst inputs)
  input logic           clk,                    // To i_fifo of fifo.v, ...
  input logic [7:0]     din,                    // To i_fifo of fifo.v
  input logic           rst_n,                  // To i_fifo of fifo.v, ...
  // End of automatics
  /*AUTOOUTPUT*/
  // Beginning of automatic outputs (from unused autoinst outputs)
  output logic [7:0]    dout                    // From i_fifo of fifo.v
  // End of automatics
);

  /*AUTOLOGIC*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  logic [7:0]           d;                      // From i_fifo of fifo.v
  // End of automatics

  /* fifo  AUTO_TEMPLATE (
    .dout (d),
  ); */

  fifo #
    (.DEPTH   (24),
     .T_DATA  (logic [7:0]))
  i_fifo
    (/*AUTOINST*/
     // Outputs
     .dout                              (d),                     // Templated
     // Inputs
     .clk                               (clk),
     .rst_n                             (rst_n),
     .din                               (din));

  /* fifo  AUTO_TEMPLATE (
    .din  (d),
  ); */

  fifo #
    (.DEPTH   (24),
     .T_DATA  (logic [7:0]))
  i_fifo
    (/*AUTOINST*/
     // Outputs
     .dout                              (dout),
     // Inputs
     .clk                               (clk),
     .rst_n                             (rst_n),
     .din                               (d));                    // Templated

endmodule

module fifo #(
  parameter DEPTH = 2,
  parameter type T_DATA = logic [7:0]
) (
  input  logic            clk,
  input  logic            rst_n,
  input  T_DATA           din,
  output T_DATA           dout
);

endmodule

// Local Variables:
// verilog-typedef-regexp: "^[tT]_"
// verilog-auto-inst-param-value:t
// End:

Now, if I remove the declaration for the fifo module from the same file as the test module and place it into its own file, then you can see the expanded results here. Notice no din or dout declarations, nothing under AUTOLOGIC, and the comments in the fifo instances related to din and dout use "Interfaces" whereas before they were under "Inputs" and "Outputs"

module test
(
  /*AUTOINPUT*/
  // Beginning of automatic inputs (from unused autoinst inputs)
  input logic           clk,                    // To i_fifo of fifo.v, ...
  input logic           rst_n                   // To i_fifo of fifo.v, ...
  // End of automatics
  /*AUTOOUTPUT*/
);

  /*AUTOLOGIC*/

  /* fifo  AUTO_TEMPLATE (
    .dout (d),
  ); */

  fifo #
    (.DEPTH   (24),
     .T_DATA  (logic [7:0]))
  i_fifo
    (/*AUTOINST*/
     // Interfaces
     .din                               (din),
     .dout                              (d),                     // Templated
     // Inputs
     .clk                               (clk),
     .rst_n                             (rst_n));

  /* fifo  AUTO_TEMPLATE (
    .din  (d),
  ); */

  fifo #
    (.DEPTH   (24),
     .T_DATA  (logic [7:0]))
  i_fifo
    (/*AUTOINST*/
     // Interfaces
     .din                               (d),                     // Templated
     .dout                              (dout),
     // Inputs
     .clk                               (clk),
     .rst_n                             (rst_n));

endmodule

// Local Variables:
// verilog-typedef-regexp: "^[tT]_"
// verilog-auto-inst-param-value:t
// End:

wsnyder · 2023-11-21T22:45:35Z

@cswmeta this issue is many years old, please open a new ticket with your issue, thanks.

veripoolbot closed this as completed Jul 24, 2016

veripoolbot added the autos label Mar 14, 2020

veripoolbot assigned wsnyder Mar 14, 2020

cswmeta mentioned this issue Nov 27, 2023

Using AUTOs with parameterized type #1847

Closed

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Using AUTOs with parameterized types #1061

Using AUTOs with parameterized types #1061

veripoolbot commented May 25, 2016

veripoolbot commented Jul 24, 2016

cswmeta commented Nov 21, 2023 •

edited

wsnyder commented Nov 21, 2023

Using AUTOs with parameterized types #1061

Using AUTOs with parameterized types #1061

Comments

veripoolbot commented May 25, 2016

veripoolbot commented Jul 24, 2016

cswmeta commented Nov 21, 2023 • edited

wsnyder commented Nov 21, 2023

cswmeta commented Nov 21, 2023 •

edited