Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issue #1064

Parser doesn't understand constraint implication operator ('->')

Added by Dave Storrar about 3 years ago. Updated almost 3 years ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
% Done:

0%


Description

The following code produces a parsing error:

class testcase;
  rand bit [3:0] a, b;
  constraint c { (a == 0) -> (b == 1); }
endclass
%Error: testcase.sv:3: syntax error, unexpected '}'

I see a comment in the VParseBison.y that seems to relate to a conflict between the 2009 and 2012 SystemVerilog versions, but I'm not familiar with Bison, so can't work out what should be happening.

Hope you can help.

History

#1 Updated by Wilson Snyder about 3 years ago

I spent about 3 hours trying to fix this, sorry it's a big mess due to ambiguities in the Verilog language specification, so give me some more time. For the moment you may want to `ifndef around it.

#2 Updated by Wilson Snyder almost 3 years ago

  • Status changed from New to Confirmed

Sorry, but after days of trying this appears almost impossible to fix using the current parser. I'm going to have to abandon fixing this for the time being. If you or a Bison expert wants to provide a patch, excellent!

#3 Updated by Dave Storrar almost 3 years ago

Thanks for making the attempt, I'll just have to work-around it.

Will let you know if I find a Bison expert ;-)

Also available in: Atom