verilog-auto-assign-modport (function) is not able expand signals if they non-logic based signals(typedef) #1069
Comments
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Original Redmine Comment Is your verilog-typedef-regexp properly set? If so please send a complete standalone example showing what you get and what you expect. Thanks. |
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Original Redmine Comment Closing due to age; I presume you found the problem you were having. If not please reopen or file a new bug. |
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Author Name: Chakradhara Aradhyula
Original Redmine Issue: 1069 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Hi
Auto assign modport is not able to resolve the signals that are typedef.
Ex:
interface INTF(input bit clk, reset);
logic A;
type_def_B B;
modport master(
output A;
input B;
)
modport slave(
output B;
input A;
)
In this case, Signal B is not part of auto assign modport.
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