Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issue #1071

Array assignment and comparison don't use full array value

Added by Andrew Bardsley about 1 year ago. Updated about 1 year ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
TranslationError
% Done:

0%


Description

Comparisons of memory arrays don't yield the correct result as it seems only the 0-index elements of the arrays are compared. Also, it is possible to assign a reg from a whole array. This results in the reg getting element 0's value.

reg [3:0] array_1 [2:0];
reg [3:0] array_2 [2:0];
reg [3:0] elem;
reg array_1_ne_array_2;

// Comparisons only compare elements 0
array_1_ne_array_2 = array_1 != array_2;

// Assigns element 0
elem = array_1;

The code generated for these statements is:

   vlTOPp->top__DOT__array_1_ne_array_2 = (vlTOPp->top__DOT__array_1
                        [0U] != 
                        vlTOPp->top__DOT__array_2
                        [0U]);

    vlTOPp->top__DOT__elem = vlTOPp->top__DOT__array_1
    [0U];

Tested with version 3.884 and git 891214fa72e6b0b72e23e119266b1792efc1ea1b

Running the same example on Questasim yields:

** Error: multidim_array_compare.sv(27): Illegal assignment to type 'reg[3:0]' from type 'reg[3:0] $[2:0]': Cannot assign an unpacked type to a packed type.

multidim_array_compare.sv - Standalone failure example (837 Bytes) Andrew Bardsley, 07/05/2016 02:37 PM

t_array_compare.pl View - test_regress driver for array_compare test (466 Bytes) Andrew Bardsley, 07/13/2016 09:17 AM

t_array_compare.v - test_regress verilog source for array_compare test (1.5 KB) Andrew Bardsley, 07/13/2016 09:17 AM

History

#1 Updated by Wilson Snyder about 1 year ago

  • Status changed from New to AskedReporter

The V3Slice stage should be doing this. However as you noted your example isn't legal code - verilator doesn't error out on all possible errors.

Can you please convert this to a test_regress format test as described in the documentation that is both self checking, and passes on e.g. Questasim but fails on Verilator? Thanks

#2 Updated by Andrew Bardsley about 1 year ago

Sure.

I've attached a test_regress test. It passes with both Questasim and VCS but fails with Verilator.

#3 Updated by Wilson Snyder about 1 year ago

  • Status changed from AskedReporter to Resolved

Fixed in git towards 3.885.

#4 Updated by Wilson Snyder about 1 year ago

  • Status changed from Resolved to Closed
  • Assignee set to Wilson Snyder

In 3.886.

Also available in: Atom