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Author Name: David Rogoff
Original Redmine Issue: 1072 from https://www.veripool.org
Original Date: 2016-07-07
Original Assignee: Wilson Snyder (@wsnyder)
Hi.
Just found this. Also downloaded latest verilog-mode.el to make sure it's still an issue:
module aa;
int a,b,c;
initial begin
randcase
10 : begin
a = 1;
end
15 : begin
b = 0;
c = 5;
end
endcase // randcase
end // initial begin
endmodule // a
The text was updated successfully, but these errors were encountered:
Author Name: David Rogoff
Original Redmine Issue: 1072 from https://www.veripool.org
Original Date: 2016-07-07
Original Assignee: Wilson Snyder (@wsnyder)
Hi.
Just found this. Also downloaded latest verilog-mode.el to make sure it's still an issue:
The text was updated successfully, but these errors were encountered: