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Issue #1075

About testbench

Added by nan wu about 3 years ago. Updated about 3 years ago.

Status:
NoFixNeeded
Priority:
High
Assignee:
-
Category:
-
% Done:

0%


Description

I have learnt Verilator for a week. There still is a foolish question in my mind--how to simulate(provide input)? We write testbench in verilog when using ModelSim, does it need use SystemC/C++ to create the testbench if we use Verilator? Then the testbench will be very complex in order to test all the situations, but the authority said it just need write a touch of C code and Makefiles after synthesizable verilog is migrated to C++ or SystemC.

History

#1 Updated by Wilson Snyder about 3 years ago

  • Status changed from New to NoFixNeeded

This just came up elsewhere, so see this:

http://www.veripool.org/boards/2/topics/1931?r=1934#message-1934

BTW, usually "issues" are written for something broken, and "forums" are for questions on using something that isn't thought to be broken.

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