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About testbench #1075

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veripoolbot opened this issue Jul 14, 2016 · 1 comment
Closed

About testbench #1075

veripoolbot opened this issue Jul 14, 2016 · 1 comment
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resolution: no fix needed Closed; no fix required (not a bug)

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Author Name: nan wu
Original Redmine Issue: 1075 from https://www.veripool.org
Original Date: 2016-07-14

I have learnt Verilator for a week. There still is a foolish question in my mind--how to simulate(provide input)? We write testbench in verilog when using ModelSim, does it need use SystemC/C++ to create the testbench if we use Verilator? Then the testbench will be very complex in order to test all the situations, but the authority said it just need write a touch of C code and Makefiles after synthesizable verilog is migrated to C++ or SystemC.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-07-14T10:36:37Z

This just came up elsewhere, so see this:

http://www.veripool.org/boards/2/topics/1931?r=1934#message-1934

BTW, usually "issues" are written for something broken, and "forums" are for questions on using something that isn't thought to be broken.

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