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Issue #1078

Support for SystemVerilog foreach

Added by Xuan Guo 11 months ago. Updated 8 months ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Unsupported
% Done:

0%


Description

SystemVerilog's foreach statement provides a convenient way to iterate through unpacked/packed arrays.
Unsupported: SystemVerilog 2005 reserved word not implemented: foreach
Currently the above error is raised.

History

#1 Updated by Wilson Snyder 10 months ago

  • Category set to Unsupported
  • Status changed from New to Feature

There's a ton of different foreach's in the language. Do you have real production code using them (as opposed to something experimental)? If so can you please submit a test case (see the manual on the format) with the ones you have that are common?

#2 Updated by Xuan Guo 9 months ago

Wilson Snyder wrote:

There's a ton of different foreach's in the language. Do you have real production code using them (as opposed to something experimental)? If so can you please submit a test case (see the manual on the format) with the ones you have that are common?

I believe that according to the spec, there's only one possible construct of foreach, which iterates through array indices. This is quite useful when writing code with parameterized bit width. It is particularly useful in write-enable bits, see [here](https://github.com/lowRISC/lowrisc-chip/blob/master/src/main/verilog/chip_top.sv#L501) (from an open source project by University of Cambridge).

#3 Updated by Wilson Snyder 9 months ago

  • Status changed from Feature to Resolved
  • Assignee set to Wilson Snyder

Fixed in git towards 3.888.

Supported all but empty index syntax ",," which seems to have limited support elsewhere.

#4 Updated by Wilson Snyder 8 months ago

  • Status changed from Resolved to Closed

In 3.888 (on 2016-10-14).

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