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Question: generate statement for instances -> supported? #1078

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veripoolbot opened this issue Aug 8, 2016 · 7 comments
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Question: generate statement for instances -> supported? #1078

veripoolbot opened this issue Aug 8, 2016 · 7 comments
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@veripoolbot
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Author Name: John John John
Original Redmine Message: 1964 from https://www.veripool.org


Hello,

Does the Emacs Verilog-Mode support the "generate" statement for instances?

For Example:

genvar i;
for (i = 0; i < 5; i++)
begin
module_name instance_name(
.a (...)
.b (...)
);
end

If it's supported, could you please provide a code example?

Thank you

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-08-10T12:09:08Z


Supported in what sense? They should indent properly. They AUTO as if not in a generate which should be sufficient.

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Original Redmine Comment
Author Name: John John John
Original Date: 2016-08-10T13:24:15Z


Will AUTO_TEMPLATE work as well?

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-08-12T12:35:21Z


Try it. Please generally experiment first, then post if you are stuck.

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Original Redmine Comment
Author Name: John John John
Original Date: 2016-08-14T12:30:42Z


Here is an example:

/* tb_ad7980 AUTO_TEMPLATE (//**
// Outputs
.sdo       (adc@_din),
// Inputs
.sck       (adc_clk),
.conv      (adc_conv),
.shreg_val (shreg@_val[]),
); */

genvar i;
generate
  for (i=0; i < 32; i=i+1) begin
       tb_ad7980 #(.ID(i))
     i_tb_ad7980(//***
                 /*AUTOINST*/
		// Outputs
		.sdo			(adc7980_din),		 // Templated
		// Inputs
		.sck			(adc_clk),		 // Templated
		.conv			(adc_conv),		 // Templated
		.shreg_val		(shreg7980_val[15:0]));	 // Templated
  end
endgenerate

As you could see, the instance name contains a number (7980), which was interpreted as an instance number (not a part of the instance name).

So, how to handle the situation where a number is a part of the instance and should not be interpenetrated by AUTOs as an instance number?

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-08-14T12:44:04Z


You didn't say why this is in any way unexpected. I hypothesize you expected 1..31 for the at sign?

As documented the at sign is from the instance name. It would be impossible to expand generates as they are not known until elaboration time. If you have a simply 32 instances, an alternative is just put down 32 cells manually and let the auto expansion uniquely hook them up.

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Original Redmine Comment
Author Name: John John John
Original Date: 2016-08-15T07:08:06Z


"As documented the at sign is from the instance name" - where is it documented/described? Is in the LISP language? Is there a short manual/user guide of LISP language for Emacs Verilog-Mode users? Thank you

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-08-23T10:59:53Z


In a Verilog-mode buffer, see the Help menu Verilog topic. Or read the documentation tab on this site. http://www.veripool.org/projects/verilog-mode/wiki/Documentation

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