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Interface declaration typo gives a misleading internal error #1097

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veripoolbot opened this issue Oct 21, 2016 · 2 comments
Closed

Interface declaration typo gives a misleading internal error #1097

veripoolbot opened this issue Oct 21, 2016 · 2 comments
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed

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Author Name: Todd Strader (@toddstrader)
Original Redmine Issue: 1097 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

Instead of pointing out the bad interface instance declaration or the port map which uses the bogus interface, the interface declaration itself is called out.

Added t_intf_typo to demonstrate:
https://github.com/toddstrader/verilator-intf-err-msg

We now get:
%Error: Internal Error: t/t_intf_typo.v:6: ../V3LinkDot.cpp:336: Module/etc never assigned a symbol entry?

But no mention that fo_intf isn't a thing or that the_foo isn't the right type for foo in the port map.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-10-22T12:07:37Z

Fixed in git towards 3.889.

It still warns on the usage rather than the more obvious typo which it really should due to how it works to support an interface that is inside a generate that will later be decided to be "if"ed out.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-11-25T16:02:34Z

In 3.890.

@veripoolbot veripoolbot added area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed labels Dec 22, 2019
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed
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