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Verilator crashes when compiling a child module which accesses a struct signal in a parent module, that parent module takes a parameter, and the parameter is set to a non-default value. I'm not sure whether this is legal Verilog in the first place (I came across it as a bug inside a larger project), but it would be nice to at least get a clean error message, rather than a crash.
Example RTL:
typedef struct packed {
logic foo;
} some_struct_t;
module child ();
logic a;
assign a = bar.foo;
// note that "foo" can be replaced with any string,
// and the same error occurs
endmodule
module parent
#(
parameter some_param = 0
)
(
);
some_struct_t bar;
child c ();
endmodule
module top ();
// The parameter must be anything other than the default
parent #( 1 ) p ();
endmodule
Author Name: Ian Thompson
Original Redmine Issue: 1099 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Verilator crashes when compiling a child module which accesses a struct signal in a parent module, that parent module takes a parameter, and the parameter is set to a non-default value. I'm not sure whether this is legal Verilog in the first place (I came across it as a bug inside a larger project), but it would be nice to at least get a clean error message, rather than a crash.
Example RTL:
Output:
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