Author Name: Adrian Wise
Original Redmine Issue: 1104 from https://www.veripool.org

In SystemVerilog there is, I believe - I admit to being very new to SystemVerilog - no syntax to be able to pass parameters to an interface type when it is used in the signal list of a module.

Instead in the signal list the keyword 'interface' should be used.

See the example code, attached, which essentially lifted directly from Section 25.8 "Parameterized interfaces" of IEEE 1800-1012. (I've deleted the tasks which are not relevant to this issue, and changed a 'ref' on 'data' to 'input'/'output' in the modports so this should be supported by Verilator.)

When compiled this gives:

$ verilator -lint-only parameterized_interfaces.v
%Error: parameterized_interfaces.v:23: Unsupported: virtual interfaces
%Error: parameterized_interfaces.v:29: Unsupported: virtual interfaces
%Error: Exiting due to 2 error(s)
...
$ verilator -V
Verilator 3.888 2016-10-14 rev verilator_3_888
...

I don't think that this is an example of a virtual interface, so at the very least this is a confusing error message.

It's tempting to change, in this example, the keyword 'interface' for the type 'simple_bus', for example:

module memMod(simple_bus a);

(or use the modports simple_bus.slave / simple_bus.master as appropriate)

But this is incorrect because that's a reference to a simple_bus with default parameters - not one with the parameters for the bus that's actually connected to the CPU or memory.