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Issue #1107

Enum widths do not get reported by Verilog::SigParser

Added by Lalit Chhabra 8 months ago. Updated 7 months ago.

Status:
Closed
Priority:
Normal
Assignee:
% Done:

0%


Description

Hi, I am trying to use Verilog::SigParser to calculate sizes of system verilog data structures in my verilog code. The var() callback provides information on data structures and their members, but the width of enums does not show up in the data type in all cases. For example, when parsing the following code:

typedef enum logic [1:0] { A=2'h0, B=2'h1 } my_enum_e;

the var() callback gets the following list of arguments (comma separated):

MyParser=HASH,typedef,my_enum_e,module,,logic,,

The $data_type argument is reported as "logic", but I would expect something like "logic [1:0]". Is this intentional?

I have attached a git patch with a fix for correct data_type reporting of enums; could you please check and incorporate into the next release?

Thanks, Lalit Chhabra

0001-Provide-correct-data_type-for-enums.patch View (2.64 KB) Lalit Chhabra, 11/09/2016 07:17 PM

History

#1 Updated by Wilson Snyder 8 months ago

  • Status changed from New to Resolved
  • Assignee set to Lalit Chhabra

Great, well done.

Pushed to git towards 3.421. I'll release in about 2 weeks if nothing else comes up.

#2 Updated by Wilson Snyder 7 months ago

  • Status changed from Resolved to Closed

In 3.422.

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