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The issue is, I want to store the trace (vcd) of a submodule rather than the top module. If I run verilator with "--trace -O0", most submodules are not inlined, so I can get them from the top, like:
// trace top.v.A.B rather than top
Verilated::traceEverOn(true)
topp->__PVT__v->__PVT__A->__PVT__B->trace(vcdp, 99);
However, in the final link stage, linker complains missing B::trace(VerilatedVcdC* int, int)
What I can see is, verilator generates XXX__Trace.cc file for the top module but not submodules (although the trace function is defined in header).
Is there a way to tell verilator to emit trace for all submodules or I can have a --trace-top to define which module is the trace top?
(Please ignore #1108, I have no idea how I ended up into a private issue)
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-11-14T17:29:49Z
At present you can only trace from the top down. You can specify which modules to include/exclude using the pragmas or .vlt file described in the documentation.
If you want to make a trace-top option that sounds a reasonable enhancement, if you want to make a patch to include this, I'll take it back.
Author Name: Wei Song
Original Redmine Issue: 1109 from https://www.veripool.org
The issue is, I want to store the trace (vcd) of a submodule rather than the top module. If I run verilator with "--trace -O0", most submodules are not inlined, so I can get them from the top, like:
However, in the final link stage, linker complains missing B::trace(VerilatedVcdC* int, int)
What I can see is, verilator generates XXX__Trace.cc file for the top module but not submodules (although the trace function is defined in header).
Is there a way to tell verilator to emit trace for all submodules or I can have a --trace-top to define which module is the trace top?
(Please ignore #1108, I have no idea how I ended up into a private issue)
The text was updated successfully, but these errors were encountered: