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Can't compile with "--assert" for files with "unique casez" #1117

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veripoolbot opened this issue Dec 2, 2016 · 4 comments
Closed

Can't compile with "--assert" for files with "unique casez" #1117

veripoolbot opened this issue Dec 2, 2016 · 4 comments
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resolution: fixed Closed; fixed

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Author Name: Enzo Chi
Original Redmine Issue: 1117 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Verilator 3.886 2016-07-30 rev verilator_3_884-13-gb4a7e46

Can't compile file with "unique casez" with "--assert"

Test code:

unique_case.sv

module unique_case (
                     input bit clk,
                     input bit rst,
                     input bit [1:0] sel,
                     input bit a,
                     input bit b,
                     input bit c,
                     output bit dout
                     );

     always_ff @(posedge clk) begin
         if (rst) begin
             dout <= '0;
         end else begin
             unique casez(sel)
                 2'b00 : dout <= a;
                 2'b01 : dout <= b;
                 2'b1? : dout <= c;
             endcase // unique casez (sel)
         end
     end // always_ff @ (posedge clk)

endmodule // unique_case

Command: verilator --assert --cc unique_case.sv

Error message:

%Error: unique_case.sv:18: Unsupported tristate construct: EQ
%Error: Exiting due to 1 error(s)

Compile the same file without "--assert", everything is fine.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-12-03T19:49:56Z


Indeed had never handled inside casez, thanks for the test. Fixed in git towards 3.891.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-01-15T17:18:43Z


In 3.900.

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Original Redmine Comment
Author Name: Enzo Chi
Original Date: 2017-05-16T02:53:51Z


Tried with modified code on 3.902, it still failed. Please check the modified test code.

module unique_case (
     input bit       clk,
     input bit       rst,
     input bit [1:0] sel,
     input bit       a,
     input bit       b,
     input bit       c,
     output bit      dout
     );

     localparam logic DC  = 1'b?;

     always_ff @(posedge clk) begin
         if (rst) begin
             dout <= '0;
         end else begin
             unique casez(sel)
                 2'b00 : dout <= a;
                 2'b01 : dout <= b;
                 {1'b0, DC} : dout <= c;
             endcase // unique casez (sel)
         end
     end // always_ff @ (posedge clk)

endmodule // unique_case


@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-05-17T01:42:33Z


The example you showed for me gives an assertion failure since it does overlap.

Can you please modify test_regress/t/t_assert_casez.v and/or a similar file to show the problem and describe what result you expect? Also please open a new bug, since this one already hit a release. Thanks.

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resolution: fixed Closed; fixed
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