Author Name: alberto castella
Original Redmine Issue: 1118 from https://www.veripool.org

I am writing some system verilog testbench. However, when I create a clocking block, I obtain the following error

@

default clocking cl @(posedge clk);
default input #100ps output #100ps;
output rst_n;
output start;
output mode;
output K;
output init_delay;
output middle_delay;
output end_delay;
input addr;
input addr_en;
input dones;
endclocking

@
syntax error, unexpected IDENTIFIER, expecting '@'.

How can I solve it?