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Issue #1120

--lint-only --bbox-unsup should ignore deassign and mixed edge and activity list

Added by Galen Seitz 8 months ago. Updated 7 months ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Lint
% Done:

0%


Description

FPGA vendor models sometimes use Verilog constructs that are not supported by verilator. This makes it painful to use lint-only on a design, as it means the vendor model needs to be hacked in order to get a clean lint run. In my case I'm using a Lattice PLL model that uses deassign and a mixed edge and activity always list. These constructs generate lint errors. See the discussion here: http://www.veripool.org/boards/2/topics/2079

Attached are two regression tests that contain the problematic constructs.

t_lint_unsup_deassign.pl View (573 Bytes) Galen Seitz, 12/21/2016 08:54 PM

t_lint_unsup_deassign.v (307 Bytes) Galen Seitz, 12/21/2016 08:54 PM

t_lint_unsup_mixed.pl View (593 Bytes) Galen Seitz, 12/21/2016 08:54 PM

t_lint_unsup_mixed.v (349 Bytes) Galen Seitz, 12/21/2016 08:54 PM

History

#1 Updated by Wilson Snyder 8 months ago

  • Category set to Lint
  • Status changed from New to Resolved
  • Assignee set to Wilson Snyder

Thanks for the tests, simple enough once have those.

Fixed in git towards 3.891.

#2 Updated by Wilson Snyder 7 months ago

  • Status changed from Resolved to Closed

In 3.900.

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