--lint-only --bbox-unsup should ignore deassign and mixed edge and activity list
FPGA vendor models sometimes use Verilog constructs that are not supported by verilator. This makes it painful to use lint-only on a design, as it means the vendor model needs to be hacked in order to get a clean lint run. In my case I'm using a Lattice PLL model that uses deassign and a mixed edge and activity always list. These constructs generate lint errors. See the discussion here: http://www.veripool.org/boards/2/topics/2079
Attached are two regression tests that contain the problematic constructs.
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