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Question: verilog-auto-inst-param-value -> why not working? #1120

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veripoolbot opened this issue Jan 18, 2017 · 1 comment
Closed

Question: verilog-auto-inst-param-value -> why not working? #1120

veripoolbot opened this issue Jan 18, 2017 · 1 comment
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@veripoolbot
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Author Name: John John John
Original Redmine Message: 2123 from https://www.veripool.org

Hello,

In the shown below code, why the parameter values are not calculated in the signal widths, which are connected to the 'bfr' instance under /AUTOINST/? I mean ports din[W-1:0] and dout[W-1:0]. As you can see, a value of the verilog-auto-inst-param-value variable is 't' and the 'W' parameter has a value '8'.

module att //*
 #(parameter W = 8)
  (//** System
    input               clk,
    input               rstn,
    //** Interfaces
    input       [W-1:0] din,
    input       [W-1:0] din_vld,
    output      [W-1:0] dout

    /*AUTOINPUT*/ //**
    /*AUTOOUTPUT*/ //**

);

//////////////////////////////////////////////////////////////////////
//* DECLARATIONS
//////////////////////////////////////////////////////////////////////

/*AUTOREG*/  //**
/*AUTOWIRE*/ //**

//////////////////////////////////////////////////////////////////////
//* BUFFER
//////////////////////////////////////////////////////////////////////

/* bfr AUTO_TEMPLATE i_bfr (//**
// Parameters
.W    (W),
// Outputs
.out  (dout[]),
// Inputs
.en   (din_vld),
.in   (din[]),
); */

  bfr #(/*AUTOINSTPARAM*/
	// Parameters
	.W		(W))			 // Templated
i_bfr (//***
       /*AUTOINST*/
        // Outputs
        .out		(dout[W-1:0]),		 // Templated
        // Inputs
        .rstn		(rstn),
        .clk		(clk),
        .en		(din_vld),		 // Templated
        .in		(din[W-1:0]));		 // Templated

//-------------------------------------------------------------------

endmodule

//////////////////////////////////////////////////////////////////////
//* [EMACS]
//////////////////////////////////////////////////////////////////////
// Local Variables:
// verilog-auto-inst-param-value:t
// End:

Here is the 'bfr' module:

module bfr //*
#(parameter W  = 32)
 (//** Inputs
  input              rstn,
  input              clk,
  input              en,
  input      [W-1:0] in,
  //** Outputs
  output reg [W-1:0] out

  /*AUTOINPUT*/   //**
  /*AUTOOUTPUT*/  //**

 );

//////////////////////////////////////////////////////////////////////
//* DECLARATIONS
//////////////////////////////////////////////////////////////////////

/*AUTOREG*/
/*AUTOWIRE*/

//////////////////////////////////////////////////////////////////////
//* BUFFER
//////////////////////////////////////////////////////////////////////

//
always@(posedge clk or negedge rstn)
if (~rstn)
     out <= DV;
else if (en)
     out <= in;

endmodule
@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-01-18T13:50:06Z

As the help for verilog-auto-inst-param-value describes, the parameter must be set to a number in the instantiation.

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