Author Name: Jan Egil Ruud
Original Redmine Issue: 1121 from https://www.veripool.org

I have a rather complex problem where Verilator creates a wrong simulation result, and I've attached some basic verilog code to help explaining the issue.

In my design there is a clock bus where one clock is the main clock (clk_bus[3] in the attached code), and the other clocks are peripheral clocks (clk_bus[2:0]) that can be enabled or disabled with clk_en[2:0]. The clock source for the peripheral clock is the main clock (clk_bus[3]), which means that one of the clocks in the bus is the source of the others. I have a Incisive (Cadence) simulation that simulates this correctly, but with Verilator some registers are updated one cycle early. My workaround has been to separate the main clock from the clk_bus. Then the design simulates correctly with Verilator. Since this design is rather complex I have not been able to create a proper failing test case.