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AUTOINPUT expansion for Interfaces not working? #1125

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veripoolbot opened this issue Jan 19, 2017 · 1 comment
Closed

AUTOINPUT expansion for Interfaces not working? #1125

veripoolbot opened this issue Jan 19, 2017 · 1 comment

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@veripoolbot
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Author Name: Krishnan Balakrishnan
Original Redmine Issue: 1125 from https://www.veripool.org


Hi,

The following sample does does not generate any code for 'in1' in AUTOINPUT or AUTOREGINPUT (or AUTOWIRE) expansion though AUTOINST generates it.

---------------------PRE expansion ----------------------
package p;
typedef enum logic [1:0] {
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b10
} enum_num;
endpackage

import p::*;

module sub1 (
input p::enum_num in1,
input logic [1:0] in2
);
endmodule

module top (
/AUTOINPUT/
);

sub1 u_sub1
(/AUTOINST/);

endmodule

---------------------Post expansion ----------------------

package p;
typedef enum logic [1:0] {
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b10
} enum_num;
endpackage

import p::*;

module sub1 (
input p::enum_num in1,
input logic [1:0] in2
);
endmodule

module top (
// input p::enum_num in1,
/AUTOINPUT/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic [1:0] in2 // To u_sub1 of sub1.v
// End of automatics
);

sub1 u_sub1
(/AUTOINST/
// Interfaces
.in1 (in1),
// Inputs
.in2 (in2[1:0]));

I have to manually add 'input p::enum_num in1,' prior to AUTOINPUT or 'p::enum_num in1;' prior to AUTOREGINPUT to get it to compile.

I believe the expansion in AUTOINPUT/AUTOREGINPUT should not require the package to be defined/imported (That's a verilog compiler issue). We should be able to parse the enum type from the 'input p::enum_num in1,' statement.

Regards,
Krishnan

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-02-09T22:28:14Z


Verilog-mode needs to know what is a data type. Add e.g.

// Local Variables:
// verilog-typedef-regexp: "enum_"
// End:

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