Original Redmine Comment
Author Name: Kaushal Modi
Original Date: 2017-05-08T18:21:38Z

This is intentional from what I understand after studying the @verilog-pretty-expr@ function.

The extra space is put so that blocking and non-blocking assignments get lined up identically (though I don't know why one would have blocking and non-blocking assignments in the same block :P).

For instance, with point on "foo",

module;

    foo = 1;
    bar <= 1;
    
endmodule

running @verilog-pretty-expr@ (bound to @c-c =@), we get:

module;

    foo  = 1;
    bar <= 1;
    
endmodule

Here is the relevant code in @verilog-mode.el@:

(if (not (or (verilog-in-parenthesis-p)  ; leave attributes and comparisons alone
              (verilog-in-coverage-p)))
     (if (eq (char-after) ?=)
         (indent-to (1+ ind))	; line up the = of the <= with surrounding =
       (indent-to ind)
       ))

"Source":

Original Redmine Comment
Author Name: Kaushal Modi
Original Date: 2017-05-08T23:54:19Z

I have fixed this in "github/verilog-mode PR#15":#15

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-05-09T00:02:31Z

Looks good, thanks for digging into this.

Since you're patching, could you update it to add a proper docstring to verilog-get-lineup-indent-2 that mentions MYRE B and E (see M-x checkdoc report). Also please always have a space after ;, e.g. not ";Must" but "; Must". If you prefer I can clean these up before merging.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-05-09T16:52:45Z

Thanks, pushed to git and 2017-05-09-eb40517-vpo.