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Issue #1128

there are 2 spaces at the left side of "=" while : verilog-auto-lineup = all

Added by yun he about 3 years ago. Updated almost 3 years ago.

Status:
Closed
Priority:
Normal
Assignee:
-
Category:
Indents
% Done:

0%


Description

type the code included below:
 module;

    abci = 1;
    ef = 2;

 endmodule
I expected:
module;

    abci = 1;
    ef   = 2;

endmodule
but instead :
module;

    abci  = 1;// there are at least 2 spaces at the left side of "=" 
    ef   = 2;

endmodule

History

#1 Updated by Kaushal Modi almost 3 years ago

This is intentional from what I understand after studying the verilog-pretty-expr function.

The extra space is put so that blocking and non-blocking assignments get lined up identically (though I don't know why one would have blocking and non-blocking assignments in the same block :P).

For instance, with point on "foo",

module;

   foo = 1;
   bar <= 1;

endmodule

running verilog-pretty-expr (bound to C-c =), we get:

module;

   foo  = 1;
   bar <= 1;

endmodule

Here is the relevant code in verilog-mode.el:

(if (not (or (verilog-in-parenthesis-p)  ; leave attributes and comparisons alone
             (verilog-in-coverage-p)))
    (if (eq (char-after) ?=)
        (indent-to (1+ ind))    ; line up the = of the <= with surrounding =
      (indent-to ind)
      ))

Source

#2 Updated by Kaushal Modi almost 3 years ago

I have fixed this in github/verilog-mode PR#15

#3 Updated by Wilson Snyder almost 3 years ago

  • Category set to Indents
  • Status changed from New to Assigned

Looks good, thanks for digging into this.

Since you're patching, could you update it to add a proper docstring to verilog-get-lineup-indent-2 that mentions MYRE B and E (see M-x checkdoc report). Also please always have a space after ;, e.g. not ";Must" but "; Must". If you prefer I can clean these up before merging.

#4 Updated by Wilson Snyder almost 3 years ago

  • Status changed from Assigned to Closed

Thanks, pushed to git and 2017-05-09-eb40517-vpo.

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