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Is it simply beyond the capability of the AUTOs? I see that setting numbers to WIDTH via parameter definition in the instances and using verilog-auto-inst-param-value:t generates correct width. I'd just like to keep the widths parametric.
The text was updated successfully, but these errors were encountered:
Author Name: it we
Original Redmine Message: 2157 from https://www.veripool.org
Hi,
I have multiple instantiation of a module, where I want to join various instant output to a single bus - say bus_total = {bus_x_2,bus_x_1,bus_x_0};
Now, I'm using the following line in my template
which, at instantiation, looks fine:
I expect the port declaration too look like:
However, I get
Is it simply beyond the capability of the AUTOs? I see that setting numbers to WIDTH via parameter definition in the instances and using verilog-auto-inst-param-value:t generates correct width. I'd just like to keep the widths parametric.
The text was updated successfully, but these errors were encountered: