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Question: combine bus width from multi-instance AUTO #1130

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veripoolbot opened this issue Feb 21, 2017 · 1 comment
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Question: combine bus width from multi-instance AUTO #1130

veripoolbot opened this issue Feb 21, 2017 · 1 comment
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@veripoolbot
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Author Name: it we
Original Redmine Message: 2157 from https://www.veripool.org


Hi,

I have multiple instantiation of a module, where I want to join various instant output to a single bus - say bus_total = {bus_x_2,bus_x_1,bus_x_0};

Now, I'm using the following line in my template

    .mybus_\(.*\) (bus_total[@"(+ @ 1)"*@"vl-width"-1:@*@"vl-width"]),

which, at instantiation, looks fine:

     .mybus_x		(bus_total[1*WIDTH-1:0*WIDTH]),  //at inst 0
.
     .mybus_x		(bus_total[2*WIDTH-1:1*WIDTH]),  //at inst 1
.
     .mybus_x		(bus_total[3*WIDTH-1:2*WIDTH]),  //at inst 2

I expect the port declaration too look like:

     input [3*WIDTH-1:0*WIDTH] bus_total;

However, I get

     input [3*WIDTH-1:2*WIDTH] bus_total; //... Couldn't Merge

Is it simply beyond the capability of the AUTOs? I see that setting numbers to WIDTH via parameter definition in the instances and using verilog-auto-inst-param-value:t generates correct width. I'd just like to keep the widths parametric.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-02-21T13:09:08Z


Yes, this us too complicated. You should manually declare the wire etc.

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