Author Name: Shareef Jalloq
Original Redmine Issue: 1132 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

Hi there,

I've just switched to using SV and am struggling to modify my scripts based on Verilog::Netlist. I can't work out how to pass in the packages that should be compiled in order to resolve the 'import package::*;' references.

We have all our packages that should be compiled in a single pkg_filelist. I've tried passing this to verilog::getopt in a number of ways but the packages are always removed from ARGV and are ignored as a parameter.

I've added a testcase of what I'm trying to do. Run 'make test' from the testcase/ directory and it should be printing out the list of packages and the top level module.

What am I doing wrong? I'm expecting either the Verilog::Getopt to parse the params correctly or pass on anything to ARGV to that I can iterate over the files and load them using Verilog::Netlist->read_file.

Short version of what's in the testcase:

my $opt = new Verilog::Getopt;
$opt->parameter( qw( +libext+.sv
-sv
-f ./packages/my_package_filelist # gets ignored and lost
./packages/my_extra_pkg.sv # gets ignored and lost
+incdir+./include
-y ./verilog
) );

@argv = $opt->parameter(@argv);