module test
    (
     // Clock and Reset
     input        reset_n ,
     input        clk ,
     input [7:0]  data_in ,
     output [7:0] data_out);

    // FSM States
    localparam [10:0] FSM_IDLE_ST  = 11'b00000000001 ,
       FSM_LOAD_ST     = 11'b00000000010 ,
       FSM_CHEC_ST     = 11'b00000000100 ,
       FSM_WAIT_ST   = 11'b00000001000 ,
       FSM_SSLO_ST      = 11'b00000010000 ,
       FSM_STAR_ST       = 11'b00000100000 ,
       FSM_PROF_ST     = 11'b00001000000 ,
       FSM_STOP_ST        = 11'b00010000000 ,
       FSM_WAIT_ST     = 11'b00100000000 ,
       FSM_FINI_ST      = 11'b01000000000 ,
       FSM_ERRO_ST       = 11'b10000000000 ;

endmodule

(setq
       verilog-auto-delete-trailing-whitespace		t
       verilog-auto-endcomments         			t
       verilog-auto-indent-on-newline   			t
       verilog-auto-lineup              			'all
       verilog-auto-newline             			t
       verilog-auto-template-warn-unused			t
       verilog-auto-wire-comment				nil
       verilog-case-indent              			3
       verilog-cexp-indent              			3
       verilog-highlight-p1800-keywords 			nil
       verilog-indent-being-after-if			t
       verilog-indent-level             			3
       verilog-indent-level-module      			3
       verilog-indent-level-declaration 			3
       verilog-indent-level-behavioral  			3
       verilog-indent-level-directive   			1
       verilog-indent-lists				t
       verilog-minimum-comment-distance 			40
       verilog-tab-always-indent        			t
       )