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Unique Case + linting #1136

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veripoolbot opened this issue Mar 14, 2017 · 2 comments
Closed

Unique Case + linting #1136

veripoolbot opened this issue Mar 14, 2017 · 2 comments
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area: lint Issue involves SystemVerilog lint checking resolution: abandoned Closed; not enough information or otherwise never finished

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Author Name: Mehul Modhiya
Original Redmine Issue: 1136 from https://www.veripool.org

Hello,Everyone

While linting I am getting following warning related to case statement incomplete,

%warning-CASEINCOMPLETE:XXXX.SV:Case values incompletely covered (example pattern 0x0)

Document says that to make it complete we must add default statement into the case,but here I am using System Verilog pragma Unique, so in my logic all the case occur uniquely means default case is not needed.Is this right behaviour of verilator or am I missing something????

Thank you,
Mehul Modhiya
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-03-14T13:42:11Z

If all cases are really covered you should not get this warning. Can you attach an example, ideally in the verilator test format (please see the manual), thanks.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-06-20T23:42:36Z

Closing due to age - if you have a test case feel free to post it and I'll reopen.

@veripoolbot veripoolbot added area: lint Issue involves SystemVerilog lint checking resolution: abandoned Closed; not enough information or otherwise never finished labels Dec 22, 2019
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area: lint Issue involves SystemVerilog lint checking resolution: abandoned Closed; not enough information or otherwise never finished
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