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Interface array mismatch in length results in internal error #1143

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veripoolbot opened this issue Mar 20, 2017 · 3 comments
Closed

Interface array mismatch in length results in internal error #1143

veripoolbot opened this issue Mar 20, 2017 · 3 comments
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed

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@veripoolbot
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Author Name: Johan Bjork
Original Redmine Issue: 1143 from https://www.veripool.org

If you pass in an array of interfaces to a module that is expecting a differently sized array, you either get a silent success or a segfault, depending on whether the module expects a smaller or larger array.

module t (/*AUTOARG*/);
    localparam N = 4;
    foo_intf foos [N-1:0] ();

    baz baz_inst (.foo(foos));

    initial begin
       $write("*-* All Finished *-*\n");
       $finish;
    end

endmodule

module baz(foo_intf foo[4:0] );
endmodule

%Error: t/t_interface_array_bad.v:14: Can't find definition of 'foos__Viftop__BRA__4__KET__' in dotted signal: .foos__Viftop[4]
%Error:      Known scopes under 'foos__Viftop[4]': baz_inst, foos[0], foos[1], foos[2], foos[3]
%Error: Verilator internal fault, sorry.  Consider trying --debug --gdbbt

It seems AstUnpackArrayDType sets width "for backward compatibility" to the width of the subDType, so that makes the check in V3Width.cpp:2171 pass which otherwise seems to be the correct check to detect this.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-03-21T23:19:36Z

Fixed in git towards 3.902. Hopefully it's not oversensitive, give it a test please.

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Original Redmine Comment
Author Name: Johan Bjork
Original Date: 2017-03-22T16:30:11Z

Wilson Snyder wrote:

Fixed in git towards 3.902. Hopefully it's not oversensitive, give it a test please.

works fine for us.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-04-02T12:52:27Z

In 3.902.

@veripoolbot veripoolbot added area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed labels Dec 22, 2019
@wsnyder wsnyder mentioned this issue May 3, 2020
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed
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