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Creating an interface with parameters based of another interface causes internal error #1146

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veripoolbot opened this issue Mar 24, 2017 · 2 comments
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Creating an interface with parameters based of another interface causes internal error #1146

veripoolbot opened this issue Mar 24, 2017 · 2 comments
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@wsnyder
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed

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Author Name: Johan Bjork
Original Redmine Issue: 1146 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

module t (input clk);
    simple_bus sb_intf();
    simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple();
    initial begin
       $write("*-* All Finished *-*\n");
       $finish;
    end
endmodule

interface simple_bus #(PARAMETER = 0);
    logic dummy;
endinterface

results in

%Error: Internal Error: t/t_interface_param3.v:8: ../V3Width.cpp:1187: Unlinked varref
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-03-28T23:58:01Z

Although one simulator seems to take this and I think do the wrong thing, I don't see how this is legal under IEEE as it's not a constant function.

Added a clear error message.

Fixed in git towards 3.902.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-04-02T12:52:33Z

In 3.902.

@veripoolbot veripoolbot added area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed labels Dec 22, 2019
@wsnyder wsnyder mentioned this issue May 3, 2020
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed
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