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Issue #1151

Unsupported vpiRawTwoStateVal (etc)

Added by Calvin Maree over 2 years ago. Updated over 2 years ago.

Status:
Closed
Priority:
High
Assignee:
-
Category:
-
% Done:

0%


Description

Hello,

I have been trying to get access to the registers defined in my verilog module delay.v from the cpp testbench, but I am doing something wrong.

What I would like to update 32bit registers from the test bench.

Due to the errors, I have tried for now just to read a 1 bit register.

The error(s) I get as output when I run the sim (Vdelay) are as follows :

``` Module name: (null) %Error: /usr/local/share/verilator/include/verilated_vpi.cpp:974: vpi_get_value: Unsupported format vpiScalarVal ```

This is the case no matter the format I specify.. I have tried a few other formats from the verilated_vpi files.

I based the code on the VPI example. I suspect I am not capturing module..

Relevant part of my tb code :

  vpiHandle neg_edge_delay = vpi_handle_by_name((PLI_BYTE8*)"delay.DELAY_TEST", NULL);
  const char* name = vpi_get_str(vpiName, neg_edge_delay);
  printf("Module name: %s\n",name);  

  s_vpi_value v;
  v.format = vpiRawTwoStateVal;
  vpi_get_value(neg_edge_delay, &v);
  printf("Value of v: %d\n", *v.value.misc);

compilation :

``` verilator -Wall --cc -vpi --trace /project/fpga/simulation/src/verilog/src/delay.v --exe /project/fpga/simulation/src/verilator/delay_tb.cpp --Mdir /project/fpga/simulation/output/simulation/verilator/delay_src

make -j -C /project/fpga/simulation/output/simulation/verilator/delay_src -f Vdelay.mk Vdelay --include-dir=/project/fpga/simulation/src/verilator -I/project/fpga/simulation/src/verilog/src ```

The delay.v and delay_tb.cpp is attached.

Regards Calvin

Vdelay.h View (4.68 KB) Calvin Maree, 04/02/2017 06:03 PM

delay.v (4.51 KB) Calvin Maree, 04/02/2017 06:14 PM

delay_tb.cpp View (2.34 KB) Calvin Maree, 04/02/2017 06:14 PM

delay.v (4.51 KB) Calvin Maree, 04/02/2017 06:27 PM

History

#1 Updated by Calvin Maree over 2 years ago

Accidentally created other errors just before uploading..

#2 Updated by Wilson Snyder over 2 years ago

  • Subject changed from 'Module name: (null) \n vpi_get_value: Unsupported format <*>' to Unsupported vpiRawTwoStateVal (etc)
  • Status changed from New to AskedReporter

Sorry this was confusing for you.

1. You can't call read_and_check until after you construct the model ("new Vdelay"), as until that point nothing exists.

2. The scope for by name should be "TOP.delay.DELAY_TEST", you can call Verilated::internalsDump() to see what the hierarchy is.

3. vpiRawTwoStateVal isn't supported, use e.g. vpiIntVal. If you really need vpiRawTwoStateVal it would be a fairly easy fix to verilated_vpi.cpp, if you'd like to try a patch I'll integrate it back. I'm renaming the bug to assume that.

If you have additional problems can you please use the verilator test format as described in the manual? This makes it much quicker to setup and debug, and also makes it easy to run under other simulators presuming you have something else. Thanks.

#3 Updated by Calvin Maree over 2 years ago

Hi Wilson,

Thanks for the reply.

I initially thought that maybe the type that I was supposed to use was 'vpiRawTwoStateVal', I have no specific desire to use it.. :)

I have made the changes as suggested. I have some conceptual questions if you don't mind.

I seem to be capturing a value from the 32 bit register when using:

 v.format = vpiIntVal;
  vpi_get_value(neg_edge_delay, &v);
  printf("Value of v: %d\n", v.value.integer);

but the result is always 0 no matter what the value I set it to (using parameters).

Is this behaviour expected? If it is a bug I wil create a test as you describe.

Regards Calvin

#4 Updated by Wilson Snyder over 2 years ago

You won't see the values until at least the initial blocks have executed (you called eval once), so I suspect that's the problem.

#5 Updated by Calvin Maree over 2 years ago

Thanks, that solves it.

I apologize for the waste-of-time type questions. Once you know the answer it seems quite obvious.

Not to be rude, but the intricacies of VPI-use in the documentation would go a long way for new-comers that need to port some Verilog testbenches to CPP.

If you think its a good idea, we should create some slides or something to capture just that, for verilog test-benchers to more easily understand how to setup the testbench to interact with the Verilog variables. we could include what the limitations of the VPI implementation are etc etc.

Your input has been greatly appreciated.

Regards Calvin

#6 Updated by Wilson Snyder over 2 years ago

  • Status changed from AskedReporter to Closed

Fair point, I updated the examples.

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