Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Parameter arrays in module parameter port list #1152

Closed
veripoolbot opened this issue Apr 3, 2017 · 3 comments
Closed

Parameter arrays in module parameter port list #1152

veripoolbot opened this issue Apr 3, 2017 · 3 comments
Assignees
@wsnyder
Labels
resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

Comments

@veripoolbot
Copy link
Contributor

Author Name: Adrian Wise
Original Redmine Issue: 1152 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

System verilog parameter arrays can't be passed to modules:

module a #( parameter int p[4] = '{1, 2, 3, 4} );
endmodule

module b;
    localparam int c[4] = '{5, 6, 7, 8};
    a #(.p(c)) i_a ();
endmodule

results in:

%Error: array_parameters.sv:6: Expecting expression to be constant, but variable isn't const: c
%Error: array_parameters.sv:6: Can't convert defparam value to constant: Param p of i_a
%Error: Exiting due to 2 error(s)

I'm using:

Verilator 3.902 2017-04-02 rev verilator_3_902
@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-04-28T10:25:16Z

The parameter-value simulator doesn't support arrays at present. Looks to be a bit of work, stay tuned.

@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-04-29T02:35:19Z

Fixed in git towards 3.903. The fix for now is a bit simple, it will work with simple arrays, but likely more complicated cases will break.

@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-06-22T22:38:28Z

In 3.906.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees

@wsnyder wsnyder

Labels
resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@wsnyder @veripoolbot